The present invention relates to a semiconductor memory device and, particularly, to technology that can be effectively adapted to a static random access memory (hereinafter referred to as SRAM) which is constituted by forming bipolar transistors and complementary MOSFETs (hereinafter referred to as CMOSs) in an integrated form on the same semiconductor substrate.
A Bi-CMOS has been described in, for example, "Nikkei Electronics" published by Nikkei McGrow-Hill Co., Mar. 10, 1986, pp. 199-217. According to the above literature, the memory cell is constituted by a flip-flop type memory cell made of polysilicon having a high resistance load, and peripheral circuits such as the address circuit and the timing circuit are constituted by Bi-CMOS composite switching circuits in order to accomplish an SRAM which operates at high speeds while consuming small amounts of electric power.
According to Japanese Patent Laid-Open No. 202858/1989 (corresponds to U.S. patent application Ser. No. 274,490, filed in the U.S.A. on Nov. 22, 1988, inventors: Meguro et al., assignee: Hitachi, Ltd.), the memory cells in the CMOS-constituted SRAM are constituted by fully CMOS-type memory cells constituted by two CMOS inverters whose inputs and outputs are cross-coupled to each other, though they are not Bi-CMOSs. The above publication further describes an SRAM which includes fully CMOS-type memory cells in a highly integrated form by forming the source-drain regions and channel regions of p-channel MOSFETs of the CMOS inverters using a polysilicon film.
Moreover, U.S. Pat. No. 4,902,640 (Sachitano et al: Date of Patent, Feb. 20, 1990) discloses a Bi-CMOS which includes a vertical npn bipolar transistor having a base drawing layer made of p.sup.+ -type polysilicon formed to surround a p-type intrinsic base region, an n-type emitter region provided in the intrinsic base region, and an emitter drawing layer made of n.sup.+ -type polysilicon connected to the n-type emitter region. The above bipolar transistor having independent polysilicon layers as base and emitter drawing layers is also called double-polysilicon self-aligned transistor and features high-speed operation.